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description the A8670 is a synchronous buck converter capable of delivering up to 2 a. the A8670 utilizes valley current mode control, allowing very short on-times to be achieved. this makes it ideal for applications that require very low output voltages relative to the input voltage, combined with high switching frequencies. valley current mode control inherently provides improved transient response over traditional switcher schemes, through the use of a voltage feedforward loop and frequency modulation during large signal load changes. the A8670 includes a comprehensive set of diagnostic flags, allowing the host platform to react to a myriad of different conditions. a fault output indicates when either the temp- erature is becoming unusually high, or a single point failure has occurred; for example, the switching node (lx) shorted to ground, or the timing resistor going open-circuit. a power ok (pok) output is also provided after a fixed delay, to indicate when the output voltage is within regulation. the A8670 is a rugged solution, offering protection against input undervoltages, A8670-ds, rev. 2 features and benefits ? high efficiency integrated fets optimized for lower duty cycle voltage conversion: 180 m high side, 40 m low side ? adjustable output voltage, down to 0.6 v ? extremely short minimum controllable on-time; example: allows 12 v conversion to 0.6 v at >1 mhz ? reference accuracy of 1% throughout temperature range ? f a u l t and power ok pins for operating and protection modes: ? normal operation ? v fb low or high ? overcurrent ? uvlo ? thermal warning prior to tsd ? thermal shutdown (tsd) ? lx?gnd short protection ? timing resistor open circuit protection applications ? servers ? point of load supplies ? network and telecom ? storage fixed frequency, 2 a synchronous buck regulator with fault warnings and power ok package: 20-contact qfn with exposed thermal pad (suffix es) typical application diagram v in = 12 v, v out = 1.2 v, and f sw = 700 khz for additional examples, see the typical applications section A8670 approximate size continued on the next page? continued on the next page? v in 12 v boot vin ton ilim lx c1 c2 ss c5 10 f f 10 nf c6 100 nf 10 nf vout 1.2 v c3 r6 l1 3.6 h 10 f c4 10 r1 63.4 k A8670 en pok fault v p ull-up agnd pgnd pok fault r5 10 k 10 k c7 1 nf r3 20 k r2 20 k r4 12 k c8 39 pf comp fb bias
fixed frequency, 2 a synchronous buck regulator with fault warnings and power ok A8670 2 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com absolute maximum ratings characteristic symbol notes rating unit vin, ton, and en pin voltage v i with respect to gnd ?0.3 to 18 v lx pin voltage v lx with respect to gnd ?0.6 to v in + 0.3 v t < 50 ns, with respect to gnd ?1.0 v boot pin voltage v boot with respect to gnd v lx ? 0.3 to v lx + 8.0 v bias pin voltage v bias ?0.3 to 8.0 v all other pins ? ?0.3 to 7.0 v operating ambient temperature t a e temperature range ?40 to 85 oc maximum junction temperature t j (max) 150 oc storage temperature t stg ?55 to 150 oc selection guide part number packing* A8670eestr-t 7-in. reel, 1500 pieces/reel, 12-mm carrier tape *contact allegro ? for additional packing options output overvoltages, overtemperature, output overloads, short- circuits, current source overloads and any single point failures. the A8670 is extremely flexible, with external loop compensation, on-time select (switching frequency), programmable soft-start, and current limit. the selectable pulse-by-pulse current limit avoids the requirement to oversize the inductor to cope with large fault currents. the switching frequency can be chosen, between 200 khz and 1 mhz. the device package (es) is a 20-contact, 4 mm 4 mm, 0.75 mm nominal overall height qfn with exposed thermal pad. the package is lead (pb) free, with 100% matte tin leadframe plating. description (continued) features and benefits (continued) ?adjustable switching frequency and current limit to optimize efficiency and external component sizing ?externally adjustable soft-start time ?shutdown supply current only 1 a ?pre-bias start-up capability ?input voltage range: from 7 to 16 v table of contents functional block diagram 3 pin-out diagram and terminal list 4 functional description 7 basic operation 7 output voltage selection 7 switch on-time and switching frequency 7 inductor selection 8 output capacitor selection 9 input capacitor selection 9 soft-start and output overloads 10 fault handling and reporting 11 control loop 13 control loop design approach 14 thermal considerations 17 regulator efficiency 18 layout 19 typical applications 20 package outline drawing 26
fixed frequency, 2 a synchronous buck regulator with fault warnings and power ok A8670 3 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 0.6 v ref + - control logic on timer regulator comparator off timer soft start and delay driver linear regulator fault reporting and shutdown vin uvlo tsd fb ov vin en pgnd agnd ton boot ss sleep circuit + - g m amplifier bias driver + - current amplifier overvoltage comparator 0.69 v ref fb uv tot fb ov + - comp pok fb uv + - fb fb lx bias ilim undervoltage comparator offset 0.54 v ref fault functional block diagram thermal characteristics may require derating at maximum conditions, see application information characteristic symbol test conditions* value unit package thermal resistance (junction to ambient) r ja on 4-layer pcb based on jedec standard 37 oc/w package thermal resistance (junction to pad) r jp 2 oc/w *additional thermal information available on the allegro website
fixed frequency, 2 a synchronous buck regulator with fault warnings and power ok A8670 4 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com terminal list table number name function 1,2,20 pgnd power ground. connect to common ground. 3 vin power input for the control circuits and the drain of the internal high-side mosfet. this pin must be locally bypassed (see typical applications section circuit diagrams). 4 bias internal bias decoupling capacitor. refer to the see typical applications section circuit diagrams, for recommended capacitors. 5ton on-time pin. the resistor connected between this pin and vin defines the on-time of the regulator. this in turn defines the switching frequency for a given output voltage. 6,19 agnd analog ground. connect to common ground. this pin should be used as the fb resistor divider ground reference for optimal accuracy (see typical applications section circuit diagrams). 7 comp output of the error amplifier and compensation node. connect a series r-c network from this pin to gnd for control loop regulation. 8fb feedback input pin of the error amplifier. connect a resistor divider from the converter output voltage node, vout, to this pin to set the converter output voltage. 9ss soft-start ramp pin. the capacitor connected to this pin defines the rate of rise of the output voltage and the effective inrush current. 10 pok open drain power okay (power good) output. this pin will be a logic low if any fault (as defined in table 3) occurs, other than an overtemperature condition (t j > 140c). 11 f a u l t open drain f a u l t output. this pin will be logic low if the on-time exceeds a certain value, if the lx node is shorted to ground, or if the thermal shutdown threshold has been reached (t j > 160c). see table 3. 12 boot high-side gate drive supply input. this pin supplies the drive for the high-side switching mosfet switch. connect a 10 nf ceramic bootstrap capacitor between boot and lx. 13,14, 15,16 lx the source of the internal high-side switching mosfet. the output inductor and boot capacitor should be connected to this pin (see typical applications section circuit diagrams). 17 en enable pin. this pin is a logic input that turns the converter on or off. when en > v enhi , the part turns on. 18 ilim pulse-by-pulse current limit setting. leave this pin unconnected for maximum current from the regulator, or set this pin to gnd for 50% current reduction. ?pad exposed pad of the package provides both electrical contact to the ground and good thermal contact to the pcb. this pad must be soldered to the pcb for proper operation and should be connected to the ground plane by through-hole vias. see layout section for further details. pad 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 pgnd agnd ilim en lx agnd comp fb ss pok pgnd pgnd vin bias ton lx lx lx boot fault pin-out diagram
fixed frequency, 2 a synchronous buck regulator with fault warnings and power ok A8670 5 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com continued on the next page? electrical characteristics 1 valid at t j = ?20c to 125c and v in = 12 v; unless otherwise specified characteristics symbol test conditions min. typ. max. unit general input voltage range v in 7 ? 16 v input quiescent current i in v en = 5 v, v fb = 1.2 v, no switching ? ? 4 ma v in = 16 v, v en = 0 v ? 1 10 a feedback voltage v fb 7.0 v v in 16 v, v fb = v comp 0.594 0.600 0.606 v maximum switching frequency f sw(max) ? 1000 ? khz minimum switching frequency f sw(min) ? 200 ? khz on-time tolerance t on r ton = 60 k ?10 ? 10 % maximum on-time period t on(max) 2.5 3.5 4.5 s minimum on-time period t on(min) ?5090ns minimum off-time period t off(min) ? ? 350 ns high-side mosfet on-resistance r ds(on)hs i ds = 0.2 a ? 180 ? m high-side mosfet leakage current 2 i lkghs v ds = 12 v, en = low ? ? 2 a low-side mosfet on-resistance r ds(on)ls i ds = 0.2 a ? 40 ? m low-side mosfet leakage current 2 i lkgls v ds = 12 v, en = low ? ? 3 a soft start source current 2 i ss v ss > v sspwm ? ?10 ? a soft start threshold v sspwm v ss rising ? 600 ? mv soft start ramp time t ss c ss = 10 nf ? 600 ? s amplifier and power stage gain feedback input bias current 2 i fb v fb = 0.6 v ? 50 250 na error amplifier open loop voltage gain a vea ?61?db error amplifier transconductance g mcomp i comp = 20 a 600 800 1000 a/v error amplifier maximum source/sink current 2 i comp(max) v fb = v fb0 0.4 v ? 52 ? a comp voltage to current gain g mpower ? 1.3 ? a/v enable enable high threshold v enhi 1.8 ? ? v enable low threshold v enlo ? ? 0.8 v enable hysteresis v enhys 150 250 ? mv enable current 2 i en v en = 3.3 v ? 50 ? a
fixed frequency, 2 a synchronous buck regulator with fault warnings and power ok A8670 6 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics 1 (continued) valid at t j = ?20c to 125c and v in = 12 v; unless otherwise specified characteristics symbol test conditions min. typ. max. unit fault reporting and power ok undervoltage threshold (rising) pok hi feedback voltage relative to reference voltage, pok = high 85 90 95 % undervoltage hysteresis pok hys pok= low ? 5 ? % overvoltage threshold (rising) pok lo feedback voltage relative to reference voltage, pok = low 110 115 120 % pok rising delay pok delay ?90? s f a u l t overtemperature t ot temperature rising ? 140 ? c f a u l t overtemperature hysteresis t othys fault release = t ot ? t othys ?20?c pok and f a u l t output voltage v pok i pok = 10 ma, fault asserted ? ? 500 mv minimum vin for correct operation of pok and f a u l t v inpok pok and f a u l t pull-up of 2 k to 5 v ? 3.5 ? v pok and f a u l t leakage 2 i pok v pok = 5.5 v, fault not asserted ? ? 1 a protection pulse-by-pulse valley current limit i lim ilim = open 2.1 2.7 3.3 a ilim = gnd 1.0 1.30 1.6 a hiccup overload duration t hicoc valley current limit reached ? 50 ? s hiccup shutdown duration t hicsd ? 300 ? s pulse-by-pulse negative valley current limit i nlim load acting as a current source ?700 ? ?500 ma high-side switch protection current i hipro lx node short-circuited to gnd ? 9 ? a high-side switch protection voltage v hipro lx node short-circuited to gnd 1.8 2.0 2.2 v vin undervoltage lockout v uvlo v in rising 6.0 6.4 6.8 v vin undervoltage lockout hysteresis v uvlohys ? 400 ? mv thermal shutdown threshold t sd temperature rising ? 160 ? c thermal shutdown hysteresis t sdhys recovery = t sd ? t sdhys ?15?c 1 specifications throughout the junction temperature, t j , range of ?20oc to 125oc are assured by design and characterization unless otherwise noted. 2 positive current is into the node or pin, negative current is out of the node or pin.
fixed frequency, 2 a synchronous buck regulator with fault warnings and power ok A8670 7 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com functional description basic operation at the beginning of a switching cycle, the high-side switch is turned on for a duration determined by the current flowing into ton. the magnitude of current is determined by the value of the input voltage and the value of the on-time resistor (rton, r1 in the typical applications section circuit diagrams). during the on-time period, the current builds up through the inductor at a rate determined by the voltage developed across it and the inductance value. when the on-time period elapses, the output of an rs latch resets, turning off the high-side switch. after a small dead-time delay, the low-side switch is turned on. the current through the inductor decays at a rate determined by the output voltage and the inductance value. the current is sensed through the low-side switch and is compared to the cur- rent demand signal . the current demand signal is generated by comparing the output voltage (stepped down to the fb pin) with an accurate reference voltage. when the current through the low-side switch drops to the current demand level, the low-side switch is turned off. after a further dead-time delay, the high-side switch is turned on again, and the process is repeated. output voltage selection the output voltage (v out ) of the converter is set by selecting the appropriate feedback resistors using the following formula: v out v fb i fb 1 ++ = r 5 r 6 r 5 r 6 r 5 + r 6 (1) where: v fb is the reference voltage, r5 and r6 are as shown in the typical applications section circuit diagrams, and i fb is the reference bias current. it is important to consider the tolerance of the feedback resistors, because they directly affect the overall setpoint accuracy of the output voltage. it is also important to consider the actual resistor values selected and consider the trade-offs. high value resistors will minimize the shunt current flowing through the feedback network, enhanc- ing efficiency. however, the offset error produced by the refer- ence bias current will increase, affecting the regulation. in addi- tion, high value resistors are more prone to noise pick-up effects which may affect performance. as some kind of compromise, it is recommended that r6 be in the region of 10 k . switch on-time and switching frequency the switching frequency of the converter is selected by choosing the appropriate on-time. the on-time can be estimated to a first order by using the following formula: t on v out 1 v in = f sw (2) where: v out is the output voltage, f sw is the switching frequency, and v in is the nominal input voltage. to factor-in the effects of resistive voltage drops in the converter circuit, the following formula can be used to produce a more accurate estimate of what the on-time has to be for a required switching frequency: t on v out + ( r ds(on)ls + dcr l ) v in + ( r ds(on)ls ? r ds(on)hs ) i out 1 = i out f sw (3) where: r ds(on)ls is the low-side mosfet on-resistance, r ds(on)hs is the high-side mosfet resistance, and dcr l is the inductive resistance. the switching frequency will vary slightly as the resistive voltage drops in the circuit change, either due to temperature effects or to input voltage variations. note that when selecting the switching frequency, care should be taken to ensure the converter does not operate near either the minimum on-time (50 ns) or the minimum off-time (350 ns). minimum on-times will typically occur in combinations of maximum input voltage, minimum output voltage with minimum load, and maximum switching frequency. minimum off-times will typically occur in combinations of minimum input voltage, maximum output voltage with maximum load, and maximum switching frequency.
fixed frequency, 2 a synchronous buck regulator with fault warnings and power ok A8670 8 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com the t on from either of the above formulae can be used to deter- mine the ton resistor value, r ton (r1 in typical applications section circuit drawings): r ton t on ? 8 10 ?9 25 10 ?12 ( v in ? 0.67) ? 500 = (4) table 1 provides preferred resistor values for a given output voltage at target switching frequencies of 500 khz, 700 khz, and 1 mhz: table 1. recommended rton resistor values switching frequency, f sw 500 khz 700 khz 1 mhz v out (v) r ton (k ) v out (v) r ton (k ) v out (v) r ton (k ) 5.0 374 5.0 267 5.0 182 3.3 243 3.3 174 3.3 121 2.5 187 2.5 133 2.5 90.9 1.8 137 1.8 95.9 1.8 64.9 1.5 113 1.5 80.6 1.5 54.9 1.2 90.9 1.2 63.4 1.2 43.2 1.0 76.8 1.0 52.3 1.0 35.7 0.8 60.4 0.8 42.2 0.8 28.7 0.6 44.2 0.6 30.9 0.6 23.2 inductor selection the main factor in selecting the inductance value is the ripple current. the ripple current affects the output voltage ripple and current limit. a reasonable figure of merit for the ripple current (i ripp ) is 25% of the maximum load. so for a maximum load of 2 a, the peak-to-peak ripple current should be 500 ma. the maximum peak-to-peak ripple current occurs at the maxi- mum input voltage. to a reasonable approximation, the minimum duty cycle can be found: d (min) v out v in (max) = (5) the required (minimum) inductance can be found: l (min) d (min) v in ? v out i ripp = 1 f sw (6) note that the inductor manufacturer tolerances on the inductance value should be taken into account. this can be as high as 30%. it is recommended that gapped ferrite solutions be used as opposed to powdered iron solutions. this is because powdered iron cores exhibit relatively high core losses, especially at higher switching frequencies. higher core losses do have a detrimental impact on the long term reliability of the component. inductors are typically specified at two current levels: ? saturation current (i sat ) the worst case maximum peak cur- rent should not exceed the saturation current and indeed some margin should be allowed. the maximum peak current in an inductor occurs during an overload condition where the circuit operates in current limit. the typical valley current limit (i lim ) is 2.7 a. the peak current through the inductor is effectively the valley current limit plus the ripple current: i sat > i lim + i ripp (7) ? rms current (i rms ) it is important to understand how the rms current level is specified in terms of ambient temperature. some manufacturers quote an ambient whilst others quote a tempera- ture that includes a self-temperature rise. for example, if an inductor is rated for 85c and includes a self-temperature rise of 25c at maximum load, then the inductor cannot be safely oper- ated beyond an ambient temperature of 60c at full load. the rms current through the inductor should not exceed the rat- ing for the inductor, taking into account the maximum ambient temperature. the maximum rms current is effectively the valley current limit (i lim ) plus half of the ripple current: i rms (max) > i lim + i ripp / 2 (8) a final consideration in the selection of the inductor is the series resistance (dcr). a lower dcr will reduce the power loss and enhance power efficiency. the trade-off in using an inductor with a relatively low dcr is the physical size is typically larger. recommended inductors include the nr8040 or nr6045 series manufactured by taiyo yuden.
fixed frequency, 2 a synchronous buck regulator with fault warnings and power ok A8670 9 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com table 2 provides preferred inductor values for a given output voltage, 2 a output at target switching frequencies of 500 khz, 700 khz, and 1 mhz. table 2. recommended inductor values switching frequency, f sw 500 khz 700 khz 1 mhz v out (v) l ( h) v out (v) l ( h) v out (v) l ( h) 5.0 10 5.0 10 5.0 6.8 3.3 10 3.3 6.8 3.3 4.7 2.5 10 2.5 4.7 2.5 3.6 1.8 6.8 1.8 4.7 1.8 3.6 1.5 4.7 1.5 3.6 1.5 3.6 1.2 4.7 1.2 3.6 1.2 2 1.0 3.6 1.0 2 1.0 2 0.8 3.6 0.8 2 0.8 1.4 0.6 2 0.6 1.4 0.6 0.9 output capacitor selection the output capacitor has two main functions: influence the con- trol loop response (see the control loop section), and determine the magnitude of the output voltage ripple. the output voltage ripple can be approximated to: v ripp i ripp c out f sw 8 = (9) where: i ripp is the peak-to-peak current in the inductor (see the inductor selection section), and c out is the output capacitance. it is recommended that ceramic capacitors be used, taking into account: size, cost, reliability, and performance. it is imperative that ceramic type x5r or x7r are used. on no account should y5v, y5u, z5u, or similar be used, because the capacitance tolerance and the temperature stability is very poor. there is generally no need to consider the effects of heating caused by the ripple current flowing into the output capacitor. this is because the equivalent series resistance (esr) of ceramic capacitors is extremely low. when using ceramic capacitors, it is important to consider the effects of capacitance reduction due to the e-field. to avoid this voltage bias effect, it is recommended that the capacitor rated voltage be at least twice that of the actual output voltage. so for example, with a 5 v output, the capacitor should be rated to 10 v. for the majority of applications, a 20 f output capacitor is recommended. input capacitor selection the function of the input capacitor is to provide a low impedance shunt path for the current drawn by the A8670 when the high- side switch is on. this minimizes the amount of ripple current reflected back into the source supply. this reduces the potential for higher conducted electromagnetic interference (emi). in a correctly designed system, with a quality capacitor posi- tioned adjacent to the vin pin and the pgnd pin, this capacitor should supply the high-side switch current minus the average input current. during the high-side switch off-cycle, the capacitor is charged by the average input current. the effective rms current that flows in the input filter capaci- tor is: i rms v out v out i out v in v in ? 1 1 / 2 = (10) the amount of ripple voltage (v ripp ) that appears across the input terminals (vin with respect to gnd) is determined by the amount of charge removed from the input capacitor during the high-side switch conduction time. if a capacitor technology such as an electrolytic is used, then the effects of the esr should also be taken into account. the amount of input capacitance (c in ) required for a given ripple voltage can be found: c in i rms t on v ripp = (11) where: t on is the on-time of the high-side switch (see the switch on- time and switching frequency section; note that maximum ton occurs at minimum input voltage), and cin is the input filter capacitance.
fixed frequency, 2 a synchronous buck regulator with fault warnings and power ok A8670 10 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com as mentioned in the output capacitor selection section, the effects of voltage biasing should be taken into account when choosing the capacitor voltage rating. if ceramic capacitors are being used, then there is generally no need to consider the effects of esr heating. soft-start and output overloads the soft-start routine controls the rate of rise of the reference voltage, which in turn controls the fb pin, and thereby the out- put voltage (v out )(see figure 1). this function minimizes the amount of inrush current drawn from the input voltage (v in ) and potential voltage overshoot on the output rail (v out ). a soft-start routine is initiated when the enable pin (en) is high, no overvoltage exists on the output, the thermal protection cir- cuitry is not activated, and v in is above the undervoltage thresh- old. immediately after en goes high, the soft-start capacitor is charged via an internal 10 a source and pwm switching action occurs. during the soft-start ramp time (see a in figure 1), the reference is ramped from 0 up to 0.6 v, and the output voltage ( v out ) tracks the reference voltage. the pok flag is held low until the output voltage reaches 90% (typical) of the target volt- age and a delay of 90 s (typical) occurs. when an output overcurrent event occurs, the regulator imme- diately limits the valley current at a constant level on a pulse-by pulse basis. the output voltage will tend to fold back, depending on how low the output impedance is. when the output voltage drops below 85% (typical) of the target voltage, the pok flag goes low. if the overload occurs for shorter than the hiccup overload duration (<50 s; b in figure 1), the output will auto- matically recover to the target level. if the overload occurs for longer than the hiccup overload duration (> 50 s; c in figure 1), the regulator will shut down, the soft-start capacitor will be discharged, and (assuming no other fault conditions exist and the enable pin is still high) the regulator will be delayed by the hic- cup shutdown duration (d in figure 1). the hiccup shutdown duration ensures that prolonged overload conditions do not cause excessive junction temperatures to occur. after the hiccup shutdown duration has elapsed, the output voltage is again brought up, controlled by the soft-start function. however, if the overload condition still exists and still remains after the soft-start ramp time has elapsed, the regulator will shut down and the process will repeat until the fault is removed. the soft-start ramp time, t ss , can be found from the following formula: t ss c ss 0.6 10 10 ?6 = (12) where c ss is c5 in the typical applications section circuit dia- grams. although the A8670 is optimized for ceramic output capacitors, large value electrolytic capacitors can be used where either spe- cial hold-up, or power sequencing is required. note the guidelines for selecting large value capacitors in the control loop section. enable (en) soft-start (ss) output voltage load current 0 v 0 v power ok (pok) 0 v 0a 0 v soft-start ramp time <50 s 90 s pok delay 90 s pok delay 90 s pok delay valley current limit maximum load >50 s hiccup overload duration hiccup overload duration target output voltage 90% of target soft-start ramp time maximum load target output voltage > 200 s hiccup shutdown duration a a b c d 90% of target 85% of target figure 1. operation of the soft-start function
fixed frequency, 2 a synchronous buck regulator with fault warnings and power ok A8670 11 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com when selecting larger-value output capacitors, it is important that the soft-start period is appropriately scaled to take into account the charging of these capacitors. for example, if the soft-start is optimized for a 22 f ceramic output capacitor and a 2000 f capacitor is added to the output, there is every possibility that the converter will remain in an overload condition after the soft-start and the hiccup overload duration have elapsed. this mode of operation could prevent the output ever reaching the target output voltage. to demonstrate the above, consider the following example: a regulator programmed for a 5 v output, 20 f output capacitor, and a soft-start time-off of 1 ms. assume there is no load current draw until 5 v is reached. at start-up, the regulator has to charge the output capacitor. from cv = it , the charging current into the capacitor is: i = 20 f 5 / 1 ms = 100 ma now if a 2000 f capacitor is added to the output, the capacitor would require a charge current of: i = 2000 f 5 / 1 ms = 10 a in this condition, the A8670 would run into the pulse-by-pulse current limit, limiting the average charge current to 2.9 a (typ). an average current of 2.9 a, assumes a valley current limit of 2.7 a and a half ripple current of 0.2 a. this means that after the soft-start delay of 1 ms, the output voltage would only be charged to: v = 2.9 a 1 ms / 2000 f = 1.45 v after the soft-start period is completed, the output capacitor would be charged for a short duration, defined by the hiccup overload duration. then the converter would shut down and, after the hiccup shutdown duration had elapsed, would enter the start-up process again. this mode is highly undesirable and a more appropriate soft-start capacitor should be selected. the effects of adding an output capacitor with too-large value would be a condition similar to starting-up into a short-circuit across the output; where the regulator enters a hiccup mode of operation. if the output of the A8670 is pre-biased at start-up, the switcher will remain in a high impedance state until the soft-start has reached the feedback voltage ( v fb ) amplitude. this avoids the output voltage being discharged. after the soft-start threshold exceeds the fb pin voltage, pwm switching action occurs and the output voltage is brought up under the control of the soft-start circuit (see figure 2). note that when the regulator is turned off, it enters a high impedance mode (all switches off) and if the output voltage is discharged it is done so by the load (at a in figure 2). if the load does not discharge the output, the output voltage remains in a pre-biased condition. fault handling and reporting table 3 describes the action taken for particular faults including the status of the f a u l t and pok flags. 90% of target 90 s pok delay soft-start voltage less than f eedback voltage (v fb ) no pwm switching enable (en) soft-start/ hiccup (ss) output voltage 0 v power ok (pok) 0 v 0 v 0 v soft-start ramp time target output voltage pre-biased output voltage feedback voltage (v fb ) brought-up under soft-start control pwm switching load pulls the output voltage low a figure 2. operation of the soft-start function with pre-biasing
fixed frequency, 2 a synchronous buck regulator with fault warnings and power ok A8670 12 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com table 3. fault handling and reporting A8670 condition comments pok flag f a u l t flag action after fault 90% < v fb < 115% normal operation high high ? v fb < 85% during start-up, the feedback voltage (v fb ) is brought-up under control of the soft-start circuit low high ? after start-up, if an overload occurs for less than the hiccup overload duration (50 s), the regulator will maintain switching operation low high auto-recovery after start-up, if an overload occurs for greater than the hiccup overload duration (50 s), the regulator will turn off and initiate a soft-start cycle low high auto-restart under control of soft-start v fb > 115% no current sourced from load into regulator output regulator immediately turns off; when v fb is reduced to within regulation range, normal operation will resume low high auto-recovery v fb > 115% current sourced from load into regulator output regulator continues to operate, controlling to the negative valley current limit (i nlim ), ?600 ma (typ); if the source current from the load increases beyond the current limit level, although the current limit level still holds, current will flow from the load to the input, perhaps resulting in an increase in input voltage low high auto-recovery v in < 6 v (typ) regulator immediately turns off low high auto-restart under control of soft-start, when v in > 6.4 v (typ) t j > 140c (typ) regulator keeps operating; if t j < 120c (typ), f a u l t goes high high low ? t j > 160c (typ) regulator immediately turns off low low auto-restart under control of soft-start, when t j < 145c lx pin shorted to gnd the voltage across the series switch is monitored; if the voltage exceeds 2 v (typ), the regulator is latched off low low either the enable pin (en) or input voltage (v in ) must go low then high to restart under control of soft-start t on > 4 s (typ) regulator immediately turns off low low either the enable pin (en) or input voltage (v in ) must go low then high to restart under control of soft-start internal bias or bootstrap supply below the undervoltage threshold regulator immediately turns off low high auto-restart under control of soft-start when above bias and boot uvlo thresholds
fixed frequency, 2 a synchronous buck regulator with fault warnings and power ok A8670 13 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com control loop to a first order, the small-signal loop can be modeled as shown in figure 3. the control loop can be broken into two sections: power stage and error amplifier. power stage the power stage includes the output filter capacitor (c out ), the equivalent load (r load ), and: the inner current loop, pwm modulator, and power inductor, which together are modeled as a transconductance amplifier with a gain of 1.3 a / v. the signal v c , supplied to the power stage, is effectively the load current demand signal. this signal effectively controls the valley current through the inductor; the higher the load the larger the v c signal. to simplify matters, we will assume this signal controls the aver- age current through the inductor as opposed to the valley current. the effective dc gain of the power stage, without the output capacitor and load resistor, is 1.3 a / v, where the signal v c is limited to the range 0.36 to 2.75 v. the dc current is converted into v out as the current flows into the load resistor. the overall dc gain of the power stage is given as v out / v c (see figure 4). at full load, the v c signal would be 2 / 1.3 = 1.54 v. from a small-signal point of view, the power inductor behaves like a current source; the inductor can be ignored as far as the bandwidth of the loop is concerned. the output capacitor inte- grates the ripple current through the inductor, effectively forming a single pole with the output load. the power stage pole can be found: f p(ps) 1 = 2 c out r load (13) it can be seen that as the load changes, the position of the power pole changes in the frequency domain. this may seem like an issue in terms of where to optimize the loop, however, the change in load also changes the gain in the power stage, thus compensat- ing for this effect. figure 4 illustrates how the loop response of the power stage changes with a varying load. the position of f p1 and g1 is one solution, f p2 and g2 is another solution, and so forth. as the value of r load increases (reducing load), the power pole moves down in frequency and the dc gain increases. generally speaking this is not a problem, because even if the pole approaches the low frequency pole produced by the error amplifier, there is still plenty of gain in the system. in this case, while the phase margin may be greatly reduced, even to a value approaching 0, because there is sufficient dc gain in the loop it can be shown from nyquist theory that the system is condition- ally stable. the phase margin must be considered only at the 0 db crossover frequency. figure 3. 1 st order model of the small-signal control loop (see typical applications section circuit diagrams for component references) figure 4. power stage dc gain characteristic c out r load r5 r6 comp pin c7 c8 r4 fb pin v c il power stage v out error amplifier amplifier g m = 1.3 a / v g m = 800 a / v ref ro v c v out r load increasing gain (db) g1 g3 g2 f p 1 f p2 f p 3 frequency
fixed frequency, 2 a synchronous buck regulator with fault warnings and power ok A8670 14 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com it is recommended that x5r/ x7r ceramic capacitors be used, however, large-value capacitors such as electrolytic types can be used. care should be taken when selecting the value of an electrolytic capacitor. as this capacitance is increased, the power pole is pushed to such a low frequency that the gain can fall off sufficiently to cause a loop instability. if using an electrolytic capacitor, consideration should also be given to the equivalent series resistance (esr) value, because this introduces a zero with the capacitance itself. it is important to use a low-esr type capacitor. it should be noted that capacitor manufacturers usually quote an esr which is a maximum at a particular frequency (such as 100 khz) and temperature (20c). the esr does vary with frequency and temperature, plus there are tolerance effects as well. if the zero produced by the esr of the output capacitor features in the control loop, it is strongly recommended that a large tolerance be allowed. if necessary, the high frequency pole in the error amplifier can be used to negate the effects of this pole (see the error amplifier section). error amplifier the error amplifier is a transconductance amplifier. the dc gain of the amplifier is 61db (1122) and, with a g m value of 800 a / v, the effective output impedance of the amplifier can be modeled as: r o 1.4 m 1122 == 800 10 ?6 (14) the transconductance amplifier has a high dc gain to ensure good regulation. the gain is rolled off with a single pole posi- tioned at a low frequency. a zero is positioned at higher frequen- cies to cancel the effects of the main power stage pole. a second pole can be introduced which should have minimal effect on the loop response, but is useful for reducing the effects of switching noise. the low frequency pole occurs at: f p1(ea) 1 = 2 r o c 7 (15) the zero occurs at: f z(ea) 1 = 2 r 4 c 7 (16) the high frequency pole occurs at: f p2(ea) 1 = 2 r 4 c 8 (17) the potential divider formed by r5 and r6 in figure 3 effec- tively introduces a dc offset to the loop. this can be found from: v fb / v out . control loop design approach there are many different approaches to designing the feedback loop. the optimum solution is to select a target phase margin and bandwidth for optimum transient response. this typically requires either simulation software or detailed bode plot analysis to generate a solution. the particular approach described here derives a solution through a series of basic calculations. this approach aims for a simple ?20 db/decade roll off, from the low frequency error amplifier pole (f p1(ea) ) to the 0 db crossover point (f cross ). the 0 db cross- over point is aimed at a thirteenth of the switching frequency (f sw ). this factor is chosen as a compromise between good band- width and minimizing the phase lag introduced by the second power pole, which occurs between 1 / 3 and 1 / 6 of the switching frequency. in theory, this should introduce a phase margin of 90, however, in practice it will be slightly less than this, perhaps by about 5, due to the effects of the second power pole. it is recommended that the error amplifier high frequency pole should be positioned one octave below the switching frequency. this provides some attenuation of the switching ripple whilst having minimum impact on the closed loop response. to achieve a ?20 db/decade roll off, the error amplifier zero is positioned to coincide with the power pole at maximum load. figure 5 illustrates the power stage gain, the error amplifier gain, and then the combined overall loop response (power stage and error amplifier).
fixed frequency, 2 a synchronous buck regulator with fault warnings and power ok A8670 15 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com design example assuming: output voltage (v out ) = 1.5 v, maximum load (i out) = 2 a, switching frequency (f sw ) = 700 khz, and output capaci- tance (c out ) = 20 f. analyze the response at full load. 1. crossover frequency: 53.8 khz f cross 13 = = 700 10 3 (18) 2. overall dc gain (refer to figure 5): 20 log 10 v c = v out dc gain (ps) (19) = 61 db + 20 log 10 v out v fb dc gain (ea) (20) = 20 log 10 v c = v out 61 db + 20 log 10 v out v fb 61 db 20 log 10 d c gain (all) dc gain (ps) + dc gain (ea) = 52.8 db = + + + 1.5 1.54 0.6 1.5 20 log 10 (21) note: with a power stage gain of 1.3 a / v and a load of 2 a, the corresponding v c = 2 / 1.3 = 1.54 v. 3. with a 53.8 khz crossover and a 20 db /decade increase in gain, at what frequency does the gain reach 52.8 db? the ?20 db / decade roll off can be described as a single pole with this transfer function for magnitude (g): g 1 = 2 f rc (22) figure 5. power stage, error amplifier, and combined overall control loop response gain (db) gain (db) gain (db) f p(ps) f p1(ea) f p2(ea) f z(ea) f cross ?20 db / decade frequency frequency frequency power stage error amplifier overall loop dc gain (ps) dc gain (ea) dc gain (all)
fixed frequency, 2 a synchronous buck regulator with fault warnings and power ok A8670 16 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 3a. we know that at 53.8 khz the gain is 0 db (1). therefore the constant rc can be worked out: rc 1 = 2 53.8 10 3 1 = 2.96 10 ? 6 (23) 3b. a magnitude of 52.8 db = 436.5. the frequency at which a gain of 436.5 is reached is: f 1 123 hz = 2 2.96 10 ? 6 436.5 = (24) so the overall loop response objective is shown in figure 6. 4. select the rc components. 4a. the error amplifier pole (f p1(ea) ) occurs at 123 hz. therefore, c7 can be found: 1 = 2 1.4 10 6 123 c 7 1 = 2 r o f p1(ea) 1 nf = (25) 4b. the power pole (f p(ps) ) can be found, because the output capacitor (c out ) and maximum load (r load ) are known: 1 = 2 0.75 20 10 ?6 f p(ps) 1 = 2 r load c out 10 610 hz = (26) 4c. the error amplifier zero (f z(ea) ) also occurs at 10.610 khz to cancel the effects of the power pole. therefore, as c7 is known, r4 can be found: 1 = 2 1 10 ?9 10610 r 4 1 = 2 c 7 f p(ps) 15 k = (27) 4d. the error amplifier high frequency pole (f p2(ea) ) is set an octave below the switching frequency. therefore, c8 can be found: 1 = 2 15 10 3 (700 10 3 / 2) c 8 1 = 2 r 4 ( f sw /2) 30 p f = (28) 4e. using the above compensation component selection tech- nique, table 4 provides preferred component values for a given output voltage, 2 a output, at target switching frequencies of 500 khz, 700 khz, and 1 mhz. table 4. recommended r4 and c7 values switching frequency, f sw 500 khz 700 khz 1 mhz v out (v) r4 (k ) c7 (nf) v out (v) r4 (k ) c7 (nf) v out (v) r4 (k ) c7 (nf) 5.0 33 1.5 5.0 51 1.0 5.0 68 0.68 3.3 22 1.5 3.3 33 1.0 3.3 51 0.68 2.5 18 1.5 2.5 24 1.0 2.5 39 0.68 1.8 12 1.5 1.8 18 1.0 1.8 27 0.68 1.5 10 1.5 1.5 15 1.0 1.5 22 0.68 1.2 8.2 1.5 1.2 12 1.0 1.2 18 0.68 1.0 6.8 1.5 1.0 10 1.0 1.0 15 0.68 0.8 4.7 1.5 0.8 8.2 1.0 0.8 12 0.68 0.6 3.9 1.5 0.6 5.6 1.0 0.6 8.2 0.68 f cross 53.8 ?20 db / decade overall loop response, gain (db) 0.123 52.8 f p1(ea) f p(ps), f z(ea) frequency (khz) figure 6. design example objective: overall control loop response (power stage and error amplifier)
fixed frequency, 2 a synchronous buck regulator with fault warnings and power ok A8670 17 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com thermal considerations for a given set of conditions, the junction temperature of the A8670 can be estimated by carrying out a few calculations. this is important to ensure an adequate safety margin with respect to the maximum junction temperature (150c) to enhance reliabil- ity. this exercise also helps to understand the overall efficiency of the regulator. the general approach is to work out what thermal impedance (r j-a ) is required to maintain the junction temperature at a given level, for a particular power dissipation. it should be noted that this process is usually iterative to achieve the optimum solution. the following steps can be used as a guideline for determining a suitable thermal solution. first, estimate the maximum ambient temperature (t a ) of the application. second, define the maximum junction temperature (t j ). note that the absolute maximum is 150c. third, determine the worst case power dissipation. this will typically occur at maximum load and minimum v in . design example assuming: input voltage (v in ) = 12 v, output voltage (v out ) = 1.2 v, maximum load (i out ) = 2 a, switching frequency (f sw ) = 500 khz, target junction temperature (t j ) 125oc, maximum ambient temperature (t a ) = 105c, and inductive resistance (dcr l ) = 20 m . 1. the main power loss contributors are calculated separately: ? switch static losses a. estimate the r ds(on) of the high-side switch at the maximum target junction temperature: = 125 ? 25 200 200 200 10 ?3 = 0.3 = t j ? 25 r ds(on)hs(tj) r ds(on)hs(25c) 1 + 1 + (29) where r ds(on)hs(25c) is the r ds(on)hs value that can be found from the electrical characteristics table in this datasheet. b. estimate the r ds(on) of the low side switch at the given junc- tion temperature: = 125 ? 25 200 200 45 10 ?3 = 0.0675 = t j ? 25 r ds(on)ls(tj) r ds(on)ls(25c) 1 + 1 + (30) where r ds(on)ls(25c) is the r ds(on)ls value that can be found from the electrical characteristics table in this datasheet. c. estimate the duty cycle (d) by applying equation 3 (t on ): 1.2 + (0.068 + 0.02 ) 0.12 = = 12 + (0.068 ? 0.3 ) 21 2 v out + ( r ds(on)ls + dcr l ) v in + ( r ds(on)ls ? r ds(on)hs ) i out 1 = = i out f sw f sw dt on f sw 500 10 3 500 10 3 (31) d. the high side static loss can be determined: = 2 2 0.12 0.3 = 0.144 w p statichi = i 2 out d r ds(on)hs(tj) (32) e. the low side static loss can be determined: = 2 2 (1 ? 0.12) 0.068 = 0.239 w p staticlo = i 2 out 1 ? d r ds(on)ls(tj) (33) ? switching losses the combined turn on and turn off losses for both switches are calculated as: 12 2 = 2 6 10 ?9 500 10 3 2 = 0.072 w p switch v in 2 = i out 6 10 ?9 f sw 2 (34)
fixed frequency, 2 a synchronous buck regulator with fault warnings and power ok A8670 18 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com ? recirculation diode losses the recirculation diode losses (low-side switch) are calculated as: = = 0.8 2 6 10 ?9 500 10 3 = 0.005 w p recirc 0.8 i out 6 10 ?9 f sw (35) ? diode transit losses the recirculation diode losses (low-side switch) are calculated as: = = 12 2 3 10 ?9 500 10 3 = 0.036 w p transit v in i out 3 10 ?9 f sw (36) ? bias losses the supply bias losses are calculated as: = = 0.086 w p bias v in 7.2 10 ?3 (37) 2. the total losses in the A8670 can be estimated: p total = p statichi + p staticlo + p switch + p recirc + p transit + p bias (38) = 0.144 + 0.239 + 0.072 + 0.005 + 0.036 + 0.086 = 0.582 w 3. the thermal impedance required for the solution can be found: = = r ja t j ? t a p total 125 ? 105 0.582 = 34 c/w (39) for this particular solution, a high thermal efficiency board is required to ensure the junction temperature is kept below 125c. it is recommended to use a pcb with four layers. the A8670 should be mounted onto a thermal pad. a number of vias should connect the thermal pad to at least one of the internal layers and the bottom side of the pcb. both of these layers should be a ground plane. see the layout section for more information. regulator efficiency the overall regulator efficiency can be determined by including the inductor loss. in the above thermal characteristics example, the inductor resistance, dcr l = 20 m . therefore the inductor power loss can be found:: = = p l dcr l i 2 out 0.02 2 2 = 0.08 w (40) the overall regulator efficiency can be found: = = v out i out ( v out i out ) + p total + p l 1.2 2 (1.2 2) + 0.582 + 0.08 = 78. 4 % (41)
fixed frequency, 2 a synchronous buck regulator with fault warnings and power ok A8670 19 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com layout although the power dissipation in the A8670 is very low, it is recommended that the thermal pad of the device is soldered to an appropriate pad on the printed circuit board to help minimize the junction temperature and enhance the efficiency. the pcb pad should in turn be connected to the ground plane via a number of thermal vias. as a suggestion, the following could be used: sixteen vias, arranged in 4 rows of 4, with diameter 0.25 mm and spaced (pitch) 0.6 mm apart. the pcb pad as well as acting as a thermal connection, also forms the star connection for the grounding system. figure 7 illustrates the key objectives in the grounding system. the filtering capacitors: c1, c3, c4, and c6 should be connected as close as possible to their respective pins. the ground connec- tions for each of the capacitors should be returned directly to the star connection (pcb pad). again, these connections should be as short as possible. both the pgnd and agnd connections should connect directly to the pcb pad to form the star connection. the ground return connection for the feedback resistor should be kelvin-connected directly back to the star ground. note: to avoid voltage offset errors in the output voltage, the feedback resistor should not be connected to the filter capacitor or load grounds returns. the support components (c5, c7, and c8) that are ground refer- enced should be connected together locally and then a common trace used to return directly to the star connection. again, this ground should not pick-up any of the filter capacitors or load ground returns. due to the high impedance nature of the comp node, it is important to ensure the compensation components are connected as close as possible. the feedback trace from r5 and r6 to the fb pin is also a high impedance input and should be as short as possible and be placed well away from noisy connections such as lx. it is recommended to keep any ground planes well away from the lx node to avoid any potential noise coupling effects. A8670 ground plane (internal or bottom side of pcb) thermal vias A8670 support components local ?quiet? ground trace ground plane ss c7 pgnd thermal pad vin lx bias c8 c5 r4 comp agnd r6 r5 c1 c6 l1 c3/c4 figure 7. layout considerations for mounting the a8760
fixed frequency, 2 a synchronous buck regulator with fault warnings and power ok A8670 20 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com typical applications v in 12 v boot vin ton ilim lx c1 c2 ss c5 10 f f 10 nf c6 100 nf 10 nf vout 1.2 v c3 r6 l1 4.7 h 10 f c4 10 r1 91 k A8670 en pok fault v p ull-up agnd pgnd pok fault r5 10 k 10 k c7 1 nf r3 20 k r2 20 k r4 12 k c8 39 pf comp fb bias operating characteristics: v in = 12 v, v out = 1.2 v, f sw = 500 khz inductor used: taiyo yuden nr8040 4.7 h further improvements can be made to the efficiency of this circuit by: ? adding a 1 a schottky diode between the lx node and ground. ? using an inductor with a lower dcr. measured efficiency for this circuit application circuit 1 output current, i out (a) 75.0 77.0 79.0 81.0 83.0 85.0 87.0 efficiency, (%) 0 0.5 1.0 1.5 2.0 2.5 t a = 75c t a = 25c
fixed frequency, 2 a synchronous buck regulator with fault warnings and power ok A8670 21 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com operating characteristics: v in = 12 v, v out = 1.5 v, f sw = 500 khz inductor used: taiyo yuden nr8040 4.7 h further improvements can be made to the efficiency of this circuit by: ? adding a 1 a schottky diode between the lx node and ground. ? using an inductor with a lower dcr. measured efficiency for this circuit application circuit 2 output current, i out (a) 89.0 77.0 79.0 81.0 83.0 85.0 87.0 efficiency, (%) 0 0.5 1.0 1.5 2.0 2.5 t a = 75c t a = 25c v in 12 v boot vin ton ilim lx c1 ss c5 10 f f 10 nf c6 100 nf vout 1.5 v c3 r6 l1 4.7 h 10 f c4 10 r1 113 k A8670 en pok fault v p ull-up agnd pgnd pok fault r5 15 k 10 k c7 1 nf r3 20 k r2 20 k r4 15 k c8 33 pf comp fb bias c2 10 nf
fixed frequency, 2 a synchronous buck regulator with fault warnings and power ok A8670 22 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com operating characteristics: v in = 12 v, v out = 1.8 v, f sw = 500 khz inductor used: taiyo yuden nr8040 6.8 h further improvements can be made to the efficiency of this circuit by: ? adding a 1 a schottky diode between the lx node and ground. ? using an inductor with a lower dcr. measured efficiency for this circuit application circuit 3 output current, i out (a) 88.0 90.0 78.0 80.0 82.0 84.0 86.0 efficiency, (%) 0 0.5 1.0 1.5 2.0 2.5 t a = 75c t a = 25c v in 12 v boot vin ton ilim lx c1 c2 ss c5 10 f f 10 nf c6 100 nf 10 nf vout 1.8 v c3 r6 l1 6.8 h 10 f c4 10 r1 137 k A8670 en pok fault v p ull-up agnd pgnd pok fault r5 20 k 10 k c7 1 nf r3 20 k r2 20 k r4 18 k c8 27 pf comp fb bias
fixed frequency, 2 a synchronous buck regulator with fault warnings and power ok A8670 23 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com operating characteristics: v in = 12 v, v out = 2.5 v, f sw = 500 khz inductor used: taiyo yuden nr8040 10 h further improvements can be made to the efficiency of this circuit by: ? adding a 1 a schottky diode between the lx node and ground. ? using an inductor with a lower dcr. measured efficiency for this circuit application circuit 4 output current, i out (a) 88.0 90.0 92.0 80.0 82.0 84.0 86.0 efficiency, (%) 0 0.5 1.0 1.5 2.0 2.5 t a = 75c t a = 25c v in 12 v boot vin ton ilim lx c1 c2 ss c5 10 f f 10 nf c6 100 nf 10 nf vout 2.5 v c3 r6 l1 10 h 10 f c4 10 r1 187 k A8670 en pok fault v p ull-up agnd pgnd pok fault r5 31.6 k 10 k c7 1 nf r3 20 k r2 20 k r4 24 k c8 18 pf comp fb bias
fixed frequency, 2 a synchronous buck regulator with fault warnings and power ok A8670 24 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com operating characteristics: v in = 12 v, v out = 3.3 v, f sw = 500 khz inductor used: taiyo yuden nr8040 10 h further improvements can be made to the efficiency of this circuit by: ? adding a 1 a schottky diode between the lx node and ground. ? using an inductor with a lower dcr. measured efficiency for this circuit application circuit 5 output current, i out (a) 92.0 94.0 96.0 84.0 86.0 88.0 90.0 efficiency, (%) 0 0.5 1.0 1.5 2.0 2.5 t a = 75c t a = 25c v in 12 v boot vin ton ilim lx c1 c2 ss c5 10 f f 10 nf c6 100 nf 10 nf vout 3.3 v c3 r6 l1 10 h 10 f c4 10 r1 243 k A8670 en pok fault v p ull-up agnd pgnd pok fault r5 45 k 10 k c7 1 nf r3 20 k r2 20 k r4 33 k c8 15 pf comp fb bias
fixed frequency, 2 a synchronous buck regulator with fault warnings and power ok A8670 25 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com operating characteristics: v in = 12 v, v out = 5.0 v, f sw = 500 khz inductor used: taiyo yuden nr8040 10 h further improvements can be made to the efficiency of this circuit by: ? adding a 1 a schottky diode between the lx node and ground. ? using an inductor with a lower dcr. measured efficiency for this circuit application circuit 6 output current, i out (a) 92.0 94.0 96.0 84.0 86.0 88.0 90.0 efficiency, (%) 0 0.5 1.0 1.5 2.0 2.5 t a = 75c t a = 25c v in 12 v boot vin ton ilim lx c1 c2 ss c5 10 f f 10 nf c6 100 nf 10 nf vout 5.0 v c3 r6 l1 10 h 10 f c4 10 r1 374 k A8670 en pok fault v p ull-up agnd pgnd pok fault r5 73.2 k 10 k c7 1 nf r3 20 k r2 20 k r4 51 k c8 10 pf comp fb bias
fixed frequency, 2 a synchronous buck regulator with fault warnings and power ok A8670 26 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package es, 20-contact qfn 0.95 c seating plane c 0.08 21x 20 20 2 1 1 2 20 2 1 a a terminal #1 mark area coplanarity includes exposed thermal pad and terminals b exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) for reference only, not for tooling use (reference dwg-2864, excluding pad) dimensions in millimeters exact case and lead configuration at supplier discretion within limits shown c d d c reference land pattern layout (reference ipc7351 qfn50p400x400x80-21bm) all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) 4.10 0.30 0.50 4.10 0.50 bsc 0.75 0.05 2.6 2.6 0.25 +0.05 ?0.07 0.40 0.10 4.00 0.10 4.00 0.10 2.6 2.6 b pcb layout reference view
fixed frequency, 2 a synchronous buck regulator with fault warnings and power ok A8670 27 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com copyright ?2011-2012, allegro microsystems, inc. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com revision history revision revision date description of revision rev. 2 march 29, 2012 update t on(max) and various minor changes

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